Computer Science & Engineering - CAD for VLSI Design I Course, Syllabus, Eligibility, National Programme on Technology Enhanced Learning (NPTEL) , Chennai , Tamil Nadu

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About Computer Science & Engineering - CAD for VLSI Design I Course

Here are the details of Computer Science & Engineering - CAD for VLSI Design I Course including duration, Eligibility, Admission Criteria, Fees and Syllabus.

Type:- Video

Coordinators:- Prof. V. Kamakoti, Prof. Shankar Balachandran

Institute:- IIT Madras

syllabus:-

Chapters     Topics
Chapter 1    Evolution of CAD Tools
Chapter 2    Importance of Design Automation
Chapter 3    Basic Transistor Fundamentals
Chapter 4    Gate Level Modeling
Chapter 5    Higher Levels of Modeling
Chapter 6    Types of CAD Tools
Chapter 7    Verilog Quick Starter
Chapter 8    Introduction to Simulators
Chapter 9    Verilog Syntax
Chapter 10    Verilog - Operators and expressions
Chapter 11    Hierarchical Design and methodology
Chapter 12    Delay modeling
Chapter 13    Delay Modeling (contd)
Chapter 14    Blocking and Non Blocking Assignments
Chapter 15    Behavioural Modeling
Chapter 16    Verilog Tasks and Functions
Chapter 17    Memory Modeling
Chapter 18    Advanced Delay Modeling
Chapter 19    Advanced Delay Modeling (Contd)
Chapter 20    Verilog Tricks
Chapter 21    Introduction to Logic Synthesis
Chapter 22    Logic Synthesis (Contd)
Chapter 23    Logic Synthesis (Contd)
Chapter 24    Synthesis: Assignment Statements
Chapter 25    Synthesis: Arithmetic Operators
Chapter 26    Synthesis: Bit Selects
Chapter 27    Synthesis: Conditional Statements
Chapter 28    Synthesis: Case Statements
Chapter 29    Synthesis: Case Statements (Contd)
Chapter 30    Synthesis: Loops
Chapter 31    Synthesis: Local & Integer Variables
Chapter 32    Synthesis: Flip Flops with preset / clear
Chapter 33    Synthesis: Blocking Vs Non Blocking Assignments
Chapter 34    Synthesis: Unknowns and High Impedance
Chapter 35    Optimization in Synthesis
Chapter 36    Optimization in Synthesis (Contd)
Chapter 37    Introduction to Reconfigurable Computing
Chapter 38    Introduction to FPGAs
Chapter 39    Introduction to FPGAs (Contd)
Chapter 40    The Altera Quartus Flow
Lab Exercise    Lab 1
    Lab 2
    Lab 3
    Lab 4
    Lab 5
Project    Project - 8279 Display and Keyboard Controller
    Project - USART
    Project - Hough Transform

About the College

National Programme on Technology Enhanced Learning (NPTEL) is an acronym for National Programme on Technology Enhanced Learning which is an initiative by seven Indian Institutes of Technology (IIT Bombay, Delhi, Guwahati, Kanpur, Kharagpur, Madras and Roorkee) and Indian Institute of Science (IISc) for creating course contents in engineering and science.

NPTEL as a project originated from many deliberations between IITs, Indian Institutes of Management (IIMs) and Carnegie Mellon University (CMU) during the years 1999-2003. A proposal was jointly put forward by five IITs (Bombay, Delhi, Kanpur, Kharagpur and Madras) and IISc for creating contents for 100 courses as web based supplements and 100 complete video courses, for forty hours of duration per course. Web supplements were expected to cover materials that could be delivered in approximately forty hours. Five engineering branches (Civil, Computer Science, Electrical, Electronics and Communication and Mechanical) and core science programmes that all engineering students are required to take in their undergraduate engineering programme in India were chosen initially. Contents for the above courses were based on the model curriculum suggested by All India Council for Technical Education (AICTE) and the syllabi of major affiliating Universities in India.