Senior Design Engineer - Functional Verification, Hyderabad
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Here are the details of Senior Design Engineer - Functional Verification job in Xilinx. This job or placement paper has been sourced from either company website or newspaper or other media and from students who appeared for this job. User is requested to verify the data before applying for the job.
Location:- Hyderabad, India
Functional verification of the block/subsystem/chip level of FPGA Silicon designs like memory controllers, serdes and other logic
- Implement verification environment using high level verification languages like OVM/UVM
- Run Regression and Debug the failures to Closure
- Participate in Coverage and other Verification Metric Closure
- Participate in generation of V&C patterns
- Understand, execute and improve the current verification environments and flows
- Communicate and coordinate with designers and other stake-holders to verify the design correctness
- Participate in verification methodology development and implementation
- More than 7 years of industry hands-on experience in verification
- Bachelors/Masters in Electronics/Computer Engineering
- Proven experience in high level methodology based verification on block/ SoC level
- Hands-on experience with Specman(eRM)/OVM/VMM/Vera/System Verilog/C++/Perl based verification development
- Knowledge/experience of memory controllers and memory subsystems is a plus
- Knowledge/experience with formal functional verification is a plus
- Strong communication skills
- Knowledge of FPGA design and development flow is a plus
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Xilinx India Technology Services Pvt. Ltd.
Unit No. 04-01, 4th floor, Block I,
Cyber Pearl, Hitec city,
Hyderabad - 500 081
Fax : +91-40-2312-2388
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